AWG G3 PAD FOR PS3 Especificaciones Pagina 276
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- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
X24C04
Characteristics subject to change without notice. 9 of 13
REV 1.1 7/12/00
www.xicor.com
NOT RECOMMENDED
FOR NEW DESIGNS
A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10 ns
Input and output timing levels V
CC
x 0.5
5.0V
1533Ω
100pF
Output
A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Read & Write Cycle Limits
POWER-UP TIMING
Note: (4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
Symbol Parameter Min. Max. Unit
f
SCL
SCL clock frequency 0 400 kHz
T
I
Noise suppression time constant at SCL, SDA inputs 50 ns
td SCL low to SDA data out valid 0.1 0.9 µs
t
BUF
Time the bus must be free before a new transmission can start 1.2 µs
t
HD:STA
Start condition hold time 0.6 µs
t
LOW
Clock low period 1.2 µs
t
HIGH
Clock high period 0.6 µs
t
SU:STA
Start condition setup time (for a repeated start condition) 0.6 µs
t
HD:DAT
Data In hold time 0 µs
t
SU:DAT
Data In setup time 100 ns
t
R
SDA and SCL rise time 300 µs
t
F
SDA and SCL fall time 300 ns
t
SU:STO
Stop condition setup time 0.6 µs
t
DH
Data out hold time 50 300 ns
Symbol Parameter Max. Unit
t
PUR
(4)
Power-up to read operation 1 ms
t
PUW
(4)
Power-up to write operation 5 ms
- System Reference 1
- Objectives of this Manual 3
- Audience 3
- Scope of the Manual 3
- Safety Information 4
- 2 System Startup 31 6
- 3 Hardware Components 37 6
- 6 Device PowerSupply 135 7
- 7 Analog Modules 183 8
- A XICOR EEPROM Summary 267 9
- Index 269 9
- Table of Contents 10
- List Of Figures 11
- System Overview 15
- Revision History 16
- System Characterization 18
- Technical Highlights 20
- AC/DC Converters 21
- (in support rack) 21
- Major Components 23
- (as shown here) 24
- DUT Interface 25
- The Manipulator 26
- ON/OFF Unit 27
- The Cooling System 28
- The Workstation 29
- System Startup 31
- Emergency OFF 32
- Standby (red) 32
- ON (green) 32
- Running the System Software 34
- Emergency Off 36
- Hardware Components 37
- Tester Electronics 38
- 128 pins 39
- DPS Channel 1 40
- DPS Channel 2 40
- DPS Channel 3 40
- DPS Channel 4 40
- Channel Board 42
- Master Clock Generator 43
- ReferenceVoltage 43
- Generator 43
- High Precision PMU 43
- Parametric Measurement Units 45
- Pin PMU Settling Time 46
- Time for converting a 46
- High-Precision PMU 47
- Master Clock System 49
- 512-Pin Testhead 53
- Analog Clock Domain 54
- Overview of Test Heads 59
- Structure of Card Cages 60
- DUT Board Mechanical 61
- Overview of DUT Board Options 62
- Allocation of Card Cages 63
- Pad Blocks 67
- Testhead 69
- Test System Configuration 70
- Analog Dominant Configuration 74
- Overview of Filling 78
- Digital Fill Order 79
- (under investigation) 80
- Analog Fill Order 81
- DPS-Type Fill Order 86
- Pogo Pad Assignment 88
- Analog Pogo Pad Location 89
- Orientation Marker 95
- on Housing 95
- Utility, EEPROM and HPMU 97
- Possible Positions 102
- for the EEPROM 102
- Wafer Prober DUT Board and 104
- Probe Card 104
- DUT Board of Wafer Prober 105
- Seg. = Segment 107
- (Group) No. in 113
- DUT Board Performance 115
- Considerations 115
- Signal Traces 116
- Keep-out Areas 117
- Maintaining Signal Fidelity 118
- Signal Inhomogeneities 119
- Correctly Terminating Signal 120
- Terminating Output Pins 121
- Termination Checklist 122
- Reducing I/O Round-Trip Times 123
- DUT Board Design for Mixed 124
- Signal Tests 124
- Analog Ground 126
- (Ground Plane) 126
- Digital Ground 126
- Printed Circuit Board 129
- Sharp Corner 131
- Rounded Corner 131
- Device PowerSupply 135
- General Purpose Power Supply 136
- Switching DPS Voltages 138
- Ganged GPDPS Channels 138
- GPDPS Specifications 139
- Supply Voltage 140
- Supply Current 140
- Setting up Performance Ranges 141
- 20 mA –> 0 151
- 0 –> 20 mA 151
- Decoupling Recommendations 154
- Voltage Settling Times 157
- DPS channel switching into 158
- Ganging GPDPS Channels 159
- Disconnecting the DPS 162
- Routing DPS Lines 163
- Device Operation Sequence 164
- High Current Power Supply 168
- Connection to DUT Board 169
- Block Diagram 170
- HCDPS Specifications 176
- Ganging HCDPS Boards 177
- Disconnecting the HCDPS 177
- Routing HCDPS Lines 177
- HVDPS General Description 181
- HVDPS Specifications 182
- Analog Modules 183
- Waveform Generators 184
- Downloading 185
- Controlling 185
- Outputting 185
- Output Order 185
- High Speed AWGs 189
- Output Multiplexer 190
- SYNC CLK 191
- SYNC DATA 191
- Output Amplifier 193
- Attenuator 194
- Digital-to-Analog Converter 194
- Timing Generator 194
- Sequencer and Waveform Memory 195
- Front-end Module 196
- Attenuator/ 197
- AWG Instrument 201
- Waveform Digitizers 203
- Synchronization trigger 204
- Digitizing then memorizing 204
- Sampling Period 204
- Initial Discard 204
- Analog Out 205
- Synchronization 205
- Input Multiplexer 209
- Figure 93 Input Resistance 210
- Input Amplifier 214
- Analog-to-Digital Converter 214
- Sampler Overview 216
- Theory of Operation 219
- DC offset 221
- Time Interval Analyzer 225
- Single Channel 226
- Dual Channel 226
- TrigDelayCnt 228
- PW+(PW ) 228
- PD++ (PD +, PD+ ,PD ) 229
- TIA Key Specifications 233
- Input Block 238
- TIA Instrument 240
- ± the fixed 243
- Trigger signal 244
- @trigger input pin 244
- Analog module’s start timing 244
- @Analog module pin 244
- Synchronization Trigger 248
- Measurement start 249
- @DUT pin 249
- Analog signal 249
- Trigger edge setting 249
- Trigger Line, and Signal Line 250
- Synchronization Uncertainty 254
- Beginning of 258
- Tester Period 258
- Master Trigger Function 260
- Master-Slave” 261
- Appendices 265
- 266 Test Setup, January 2001 266
- XICOR EEPROM Summary 267
- NOT RECOMMENDED 268
- FOR NEW DESIGNS 268
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